A high-frequency micro electro mechanical system (hereinafter referred to as MEMS) element formed on a semiconductor substrate of silicon or the like can be formed easily by using a conventional semiconductor manufacturing process and another nanometer-fabrication process. However, it has a disadvantage that high-frequency characteristics are deteriorated because of parasitic capacitance between a signal line and a silicon substrate.
To decrease the parasitic capacitance between the signal line and the silicon substrate, it may be required to form an insulating film having a thickness of 10 μm or more for a lower layer of the signal line.
As the insulating film which is a lower layer of the signal line, a silicon oxide film (hereinafter referred to as CVD film) produced by a CVD (Chemical Vapor Deposition) method is conventionally used. Such a CVD film is hardly formed to have a thickness of 10 μm or more. Therefore, there is proposed a structure that a coated layer of a resin such as polyimide is formed on a semiconductor substrate, and a CVD film is additionally formed on it (see, for example, JP-A 2006-229282 (KOKAI)).
But, when the coated layer of the resin such as polyimide is formed on the entire top surface of the semiconductor substrate and the CVD film is formed on it, a large stress acts on the CVD film in a subsequent heating step or the like due to a difference in thermal expansion coefficient from the resin coated layer.